In the RD27 collaboration the authors have carried out system studies on the implementation of the first level calorimeter trigger processor system for the ATLAS experiment to be mounted at the Large Hadron Collider (LHC) at CERN. A demonstrator trigger system operated successfully with the RD3 and RD33 calorimeters at the full 40 MHz LHC bunch crossing (BC) rate. The prototype application-specific integrated circuits (ASICs) in this system each processed data from only a single trigger cell and its environment, which would lead to an extremely large system for ATLAS. Using eight-bit parallel data even the use of ASICs, processing multiple trigger cells would demand unacceptably large numbers of input pins and module connections. Initial studies of this I/O problem produced a solution based on asynchronous transmission of zero-suppressed and BC-tagged data on 160 Mbit/s serial links. This approach appeared to be feasible but would have introduced additional latency of about 20 BCs. Further studies have led to the design of a fully-synchronous calorimeter trigger processor system using commercial high-speed optical links. The links will terminate in multi-chip modules (MCMs) incorporating custom-designed integrated optics, and the trigger algorithms will be implemented in ASICs.
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